In the field of this invention it is known that the normal method of measuring jitter is to use an analogue based system implemented with a Phase Locked Loop (PLL) which tracks the input signal, therefore resulting in the PLL's oscillator control voltage containing imposed thereon an analogue representation of the jitter component of the input signal. This PLL oscillator control voltage signal can then be filtered and its level can be displayed. However, such an approach is subject to the disadvantages inherent in analogue circuitry, such as high cost, difficulty in achieving desired accuracy of performance through need to match exact performance of analogue components and lack of performance stability over changes in temperature and time.
Another method (known from patent publication WO 99/57842) of measuring jitter, using a digital approach, is to track the incoming signal with a PLL, to produce a very low frequency offset (e.g., 1.27 parts per million (ppm) and to count the number of coincidences of phasing for each sample period together with the time between these coincidences.
However, this approach requires separate analogue circuitry, a phase locked loop and jitter attenuator, and the input signal frequency needs to be tracked by this PLL with an extremely small offset (1.27 ppm) in order to work.
A need therefore exists for an apparatus and method for measurement of jitter wherein the abovementioned disadvantage(s) may be alleviated.